The subsystem Lola provides a port of the logic description language Lola-2 designed and implemented by Prof: Niklaus Wirth at ETH Zurich. Lola-2 uses a syntax similar to Oberon (and Component Pascal) for describing digital circuits (logic) that can be implemented for example on a Field Programmable Gate Array (FPGA). Lola texts are translated into the Hardware Description Language (HDL) Verilog. Hardware vendor specific tools must be used for mapping a Verilog program onto a particular hardware. The advantage of using Lola over Verilog is that it is much simpler and less error prone due to increased regularity and static error checking. For details about Lola-2 see the Lola-2 homepage.